Sense Amplifier Design

Regular:

- Without clock
- Dissipates static energy
- Differential pair

With clock:

- Regenerative feedback
- Schematic looks like a back to back inverter with PMOS transistors driven by sense_clk, blocking the bit and bit_bar lines; and NMOS transistor driven by sense_clk between ground and the inverter pair
- No static dissipation

Nice presentation about SRAM design:
http://www.ece.utexas.edu/~adnan/vlsi-04/lec13SRAM.ppt