VLSI - Silicon on Insulator (SOI)

SOI Benefits:

• suppression of bottom junctions
  - lower parasitic capacitance
  - faster switching and/or lower power
• full isolation
  - no latch-up
  - denser layout
  - lower interferences between the analog and digital parts of a SoC
  - lower losses in the passive components at high frequency
  - lower leakage current , enabling operation at higher temperature (250°C)
  - but : floating body effect in partially-depleted transistors
• thin active area
  - lower sensitivity to radiations ( lower SEU sensitivity in memory cells )

Overall performance improvement (at same technology node):

• 25% faster
• 50% lower power consumption
• 10% smaller die size

Link

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From IBM white paper on SOI:

• One of the areas that can store charge in a MOS switch is the area between the impurities added to a chip’s silicon and the silicon substrate itself, which is free of impurities. That area is called the “junction capacitance”. If a thin layer of an insulator, such as glass, is placed between the impurities and the silicon substrate, the junction capacitance will be eliminated and the MOS transistor will operate faster.
• Even in cases where the quality of the SOI layer has been fine for making single chips or small circuits, the MOS transistor placed on the SOI layer has continued to pose serious challenges. When a MOS transistor is placed on SOI, it is also placed next to a parallel bipolar transistor. The bipolar transistor can turn on when the MOS switch passes current through itself, i.e. base current will be supplied through the base impact ionization.
• Dropping the voltage is very effective in reducing chip power. The ability of SOI as a low power source originates from the fact that SOI circuits can operate at low voltage with the same performance as a bulk technology at high voltage.
• As an example, measured on a 4 Mb SRAM. At the same performance as bulk CMOS, SOI can reduce the chip power by 1.7-3X (depending on the switching factor of the devices).

IBM white paper on SOI

STL - Foreach style loop for map

map< string, double > token_data;

for ( map< string, double >::iterator im = token_data.begin(); im != token_data.end(); ++im )

cout << "\"" << im->first << "\" = " << im->second << endl;

Javascript - Checking if a variable is defined

The following is taken from this page.

....
However, we have found that sometimes developers don't read the documentation on how to set up a reusable piece of code, and will omit the global JavaScript variable. So when that reusable code is executed, an error message happens because the variable has not been defined.

To get around this, we have gotten in the habit of checking to see if a variable has been defined. This is actually pretty easy to do in JavaScript, but it's not something you would normally think of. The first thing we tried was:

if (globalVariable) {

But this wouldn't work. That code is actually checking to see if the defined variable globalVariable has a null value. If the variable has not been defined, that code will cause an error.

Instead, here is the code that will check for the presence of a global variable:

if (window.globalVariable) {

A global variable automatically becomes a part of the window object. So checking to see if the window object has that "property" means checking to see if the variable has been defined or not. Going into the if block means the variable has been defined and can be used as you would normally use a global variable.

State machines - Mealy vs Moore

Mealy:
The output is a function of the state of the machine and of the inputs.

Moore:
The output is a function only of the state of the machine checking.
M[OO]re => [O]utput [O]nly

advantages/disadvantages:

- Mealy often has fewer states than Moore machine since it associates outputs with transitions.
- Mealy machine can fall victim to glitchessince outputs are asynchronous.

How to write FSM in verilog
Mealy vs Moore [1]


Taken from [1].

Unix - wget

I am using wget to get archives of my blogs. I have a perl script where I call wget. This perl script is called once a week to archive the blogs. This is done by crontab. I keep the last 4 archives and delete the 5. one.

I am using wget 1.8 on a unix machine. This is the command I use:

/usr/local/bin/wget -a ${blog}.log -Dphotos1.blogger.com,blogspot.com -r -l1 -p -H -k -E http://$blogs{$blog}

$blog is the variable for the individual blog. %blogs is the hash which has the URL of the blog.
-a is used to append to the logfile $blog.log
-r is to retrieve recursively
-l is the level of recursion
-p is to download all page requisites
-H is to enable jumping to other domains
-k is to change the links to point to the local copies (convert links)
-E is to change *.cgi kind of file names to .html

I had some pictures which are somewhere in photos1.blogger.com so I wanted to include that domain together with blogspot.com where my blog is hosted to be able to get the pictures as well. But I couldn't manage to do it. If by changing some arguments I get the pictures, wget did not get files other than index.html from my blog. At the end I just gave up... Will look into it later.

perl:

In the perl code, use absolute positions of the directories and also wget. It causes problems with crontab otherwise.

crontab:

0 3 1,8,15,22 * * abs_position/arc_blogs.pl >/dev/null 2>/dev/null

Perl script is called at 3am every 1st, 8th, 15th, and 22nd days of the month.

HTML - Blockquote

Blockquote can be used to indent some partf of the text and/or change the backgound color of some paragraphs.

Now, I will indent the text below and change the background color:

Like this!

tag has these properties: style="BACKGROUND: #ddd; MARGIN-LEFT: 20px; WIDTH: 300px;"

Perl - Checking if a variable is null

code:

#!/usr/local/bin/perl -w
$string = "ali,veli,gel";
my($a1,$a2,$a3,$a4) = split(',',$string);
if($a1) {print "$a1 ne guzel\n";}
else {print "Sicar\n";}
if($a2) {print "$a2 ne guzel\n";}
else {print "Sicar\n";}
if($a3) {print "$a3 ne guzel\n";}
else {print "Sicar\n";}
if($a4) {print "$a4 ne guzel\n";}
else {print "Sicar\n";}

output:

ali ne guzel
veli ne guzel
gel ne guzel
Sicar

Interview with Intel CAD group

Last night, I had an interview with the CAD group in Intel. They are about 35 engineeris and they do phisical design CAD tools for the microprocessor group. They are located in Oregon and Santa Clara. He asked the following questions during the ~1 hour phone interview:

- What is the biggest coding project you were involved?
- What is the difference between C and C++?
- You have a class as follows:

class node
{
public:
node *l_child, *r_child;
....
}
Write the function delete_tree(node *root)... It is something like below:
{
if(root == NULL) return;
delete_tree(root->l_child);
delete_tree(root->r_child);
delete(root);
}

- What is virtual function used for in C++?
It has something to do with derived classes. If you have a pointer to a derived class and if you call a virtual function on that pointer, it goes to the correct function i.e. not to the function of the parent class. You can have an array of pointers of type *parent. Then you can construct them as being pointers to the derived classes. Then when you call a function for every element of the array, it will call the correct function for all the derived classes.
http://www.glenmccl.com/virt_cmp.htm

- You have a graph. Given a node, how do you find the total number of nodes? Each node has the information about its children.
- Explain breadth first search and depth first search.
http://www.ics.uci.edu/~eppstein/161/960215.html
Nice animation

Sense Amplifier Design

Regular:

- Without clock
- Dissipates static energy
- Differential pair

With clock:

- Regenerative feedback
- Schematic looks like a back to back inverter with PMOS transistors driven by sense_clk, blocking the bit and bit_bar lines; and NMOS transistor driven by sense_clk between ground and the inverter pair
- No static dissipation

Nice presentation about SRAM design:
http://www.ece.utexas.edu/~adnan/vlsi-04/lec13SRAM.ppt

CMOS Manufacturing

Why poly but not metal as M in MOS transistors?

The primary criterion for the gate material is that it is a good conductor. Highly-doped polysilicon is an acceptable, but certainly not ideal conductor, and it also suffers from some more technical deficiences in its role as the standard gate material. So why use polysilicon instead of a metal like aluminum? The reason is simple: in the MOSFET IC fabrication process, the gate material must be deposited prior to high-temperature steps that would melt metals. To improve the performance of the gate, some manufacturers form a silicide by blending a metal into the polysilicon. Such a silicide has better electrical properties than polysilicon but doesn't melt in subsequent processing.

link

What is latch-up?

Reasons:
- Parasitic circuit effect that causes V_DD and GND to short.
- Can result in self-destruction, at best a malfunction requiring a power cycle.
- Parasitic bipolar transistors formed between n and p MOS transistors.

Prevention:
- Latch-up is triggered by supply voltage transients which cause V_DD to overshoot or GND to dip by ~0.7V above or below the supply.
- Not likely to occur in core logic.
- You can prevent this condition by making liberal use of substrate contacts:
- Every well MUST have a substrate contact.
- Every substrate contact should be connected to metal directly to a supply pad.
- Place substrate contacts as close as possible to the source contacts.
- I/O circuitry is more susceptible and must be protected.
- Guard rings are used in the I/O pads to reduce gain of parasitic transistors.
- I/O pad design should be left to experts.

link

Sizing level shifter

Below is the schematic of a simple level shifter.

Sizing this circuit is not trivial. There is some feedback involved. I think MN1 and MN2 should be stronger than the PMOS transistors. Otherwise out does not become zero. For WP=2.5*WN, I used the following sizing for the transistors:

• MN1 : 5*WN
• MN2 : 5*WN
• MP1 : WP
• MP2 : 2*WP
• inverter : 3x standard size (NMOS=3*WN, PMOS=3*WP)
  

A stupid problem I faced during a spice simulation

* inverter subckt
.SUBCKT NOT1_911 vdd gnd bn bp in out w_n='9*WN' w_p='9*WP'
MP out in vdd bp PMOS_1 W='w_p' L=0.07u AD='0.1u*w_p' PD='2*(0.1u+w_p)' AS='0.1u*w_p' PS='2*(0.1u+w_p)'
MN out in gnd bn NMOS_1 W='w_n' L=0.07u AD='0.1u*w_n' PD='2*(0.1u+w_n)' AS='0.1u*w_n' PS='2*(0.1u+w_n)'
.ENDS NOT1_911

* level converter sub_ckt
.SUBCKT LVLCON vddh vddl gnd in out w_n='1*WN' w_p='1*WP'
$mos PMOS_1 MP1 int1 out vddh vddh $p1*w_p 0.1u
$mos PMOS_1 MP2 out int1 vddh vddh $p2*w_p 0.1u
$mos NMOS_1 MN1 int1 in gnd gnd $n1*w_n 0.1u
$mos NMOS_1 MN2 out int2 gnd gnd $n2*w_n 0.1u
$cir_cmos NOT1_911 XINV vddl gnd gnd vddl in int2
.ENDS LVLCON

The inverter inside the level converter always gets w_n=WN and w_p=WP instead of the values I give in the subckt NOT1_911. I think it is because the parameter names are same for both subckts and it creates some kind of a confusion.